Connect Tech BlueStorm Multi-port Serial Adapter Bedienungsanleitung PDF herunterladen (Seite 9)

SPECIAL FEATURE

www.eecatalog.com/pcie 7

Goldhammer: The major challenge in PCI Express is the constant

doubling of speed/bandwidth. At each generation the internal

data path must also double; there is a tremendous amount of

complexity involved in keeping the cores efficient and physically

small. Most of this work is just brute force, but there are also

demands to reduce latency and add new capabilities such as some

of the optional ECNs (Engineering Change Notices) released by

the PCI-SIG and demanded by customers and enabled by Intel

and other host processors.

Also with each new

generation, the link

training and state

machines get increas-

ingly complex. The

link training is the

automatic mechanism

where link partners

negotiate lane widths

and lane speeds; these

operate autonomously (without need for user intervention) and

must be extremely robust. Xilinx uses Bus Functional Models

(BFMs) in verification, but also uses released generations of

FPGAs and boards to prototype and test in real hardware the

behaviors of the transceivers.

Lastly, as the data rates increased to 8Gbps for PCIe Gen3,

the encoding has also changed to 128b/130b with scrambling.

This is a non-industry standard encoding compared to 8b/10b,

so this has created a lot of additional work and complexity to

switch between encoding.

EECatalog: How are you planning to leverage PCI Express 3.0?

Wiedemeier: LeCroy is providing a PCIe 3.0 protocol analyzer

and exerciser to help early adopters to be ready for the PCIe 3.0

v1 spec release at the end of the year. Our exerciser allows devel-

opers to get started testing with PCIe 3.0 host or device before

PDKs are available.

Dietrich: Most of our products currently do not need the fea-

tures that PCI Express 3.0 brings, such as CPU carrier boards,

digital I/O, multi-port serial, etc. However, we are looking for-

ward to the next generation of PCI Express for our FPGA/DSP

based products which require high-speed and high bandwidth

properties where approximately1GB/s per lane can be used.

Goldhammer: With PCIe 3.0, Xilinx is continuing to track very

closely with the PCI-SIG release schedule and Intel's roadmap

for deployment. Since the specification for 3.0 is expected to

be finalized by the end of the year, Xilinx is going to be using

a combination of soft IP and integrated blocks to support PCIe

Gen3 in Kintex-7 and Virtex-7 families.

In the market, PCIe has proliferated into pretty much all market

segments, hence Xilinx integration of PCIe hard blocks in all

FPGAs with transceivers. For PCIe Gen3, we see multi-10 Gigabit

Ethernet and 40 Gigabit Ethernet as the main drivers of PCIe

bandwidth. 100 Gigabit Ethernet is also driving PCIe bandwidth

needs. Image processing is another key driver for PCIe 3.0.

Whether medical imaging, 3D TV or HDTV, video applications

take advantage of FPGA processing capabilities and high-speed

PCIe ports. High-performance computing (HPC) in applica-

tions like oil and gas

exploration and finan-

cial applications are the

other key areas where the

demand for more PCIe

bandwidth and high-

performance is almost

insatiable.

EECatalog: What new,

leading- and bleeding-

edge technologies are you most excited about?

Wiedemeier: PCIe-based SSD technology is going to change the

whole storage environment.

Goldhammer: In PCIe, Active-State Power Management (ASPM)

is a capability where links can automatically go in and out of

low-power states to save system-level power. ASPM has run into

bumps in the road due to complexity and challenges in the defi-

nition. Power is a major system concern in the market. Xilinx is

an advocate of power-saving technologies and is excited to see

how the industry continues to adopt these optional power-sav-

ings capabilities into PCIe devices.

Virtualization is another area we are excited to see opening up.

Single-Root I/IO Virtualization (SR-IOV) has been rolled out

in servers already, but the rest of the industry is also coming

up to speed. As cloud computing becomes more pervasive, this

technology will be critical to its success.

Cheryl Berglund Coupé is Editor of EECatalog.com.

Her articles have appeared in EE Times, Electronic

Business, Microsoft Embedded Review and Win-

dows Developer’s Journal and she has developed

presentations for the Embedded Systems Conference

and ICSPAT. She has held a variety of production,

technical marketing and writing positions within technology com-

panies and agencies in the Northwest.

“PCIe-based SSD technology is

going to change the whole storage

environment.”

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 27 28

Kommentare zu diesen Handbüchern

Keine Kommentare

Connect Tech BlueStorm Multi-port Serial Adapter Bedienungsanleitung Seite 9

Kommentare zu diesen Handbüchern