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Connect Tech BlueStorm Multi-port Serial Adapter Bedienungsanleitung Seite 18

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CONTACT INFORMATION
16 • Chip-to-Chip Engineers’ Guide to PCI Express Solutions 2011
PLDA
TECHNICAL SPECS
V PCIe IP core in synthesizable Verilog RTL encrypted
or clear source code, compliant with the PCIe Base
3.0 Draft Specification, rev.0.9
V Supports Gen3 (8.0 GT/sec), Gen2 (5.0 GT/sec) and
Gen1 (2.5 GT/sec) speeds at x1, x2, x4 and x8 lanes
withfull backwards compatibility
V PIPE 3.0 interface to FPGA PHY/transceivers at 32-
bit/250Mhz in Gen3 mode
V Multiple user interface options including Transmit/
receive (Tx/Rx), Transaction Layer bypass, EZDMA
multi-channel DMA and AMBA 4 AXI
Win the Race to PCIe Gen3
with PLDA IP Solutions
OS Support: Windows and Linux
Bus Interface: PCI Express
PLDA PCI Express 3.0 IP for ASIC and FPGA provides full
PCIe Gen 3 functionality from the trusted leader in PCIe
IP solutions. PLDA has over 15 years of design experi-
ence with PCI interfaces, ensuring first-time-right design
success. PLDA’s PCIe Gen 3 IP solutions provide:
V Seamless ASIC and FPGA integration, allowing you to
design for FPGA and painlessly port to ASIC
V A broad range of user interfaces to answer simple to
more complex design requirements
V Quick and reliable customization to ensure the IP will
fit your specific needs
V A free evaluation program that includes the same
deliverables and technical support as the licensed IP
V Industry-acclaimed technical support provided by the
IP team
IP Building Blocks
IP Building Blocks
CONTACT INFORMATION
PLDA
2570 North First St. , Suite 218
San Jose, CA 95131
USA
Telephone (408) 273 4528
sales@plda.com
www.plda.com
PCI Express Solutions ONLINE
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